![Help please: When a button is pressed, the light should stay on for 10 clock cycles and then turn off however the light stays on indefinitely... : r/VHDL Help please: When a button is pressed, the light should stay on for 10 clock cycles and then turn off however the light stays on indefinitely... : r/VHDL](https://preview.redd.it/help-please-when-a-button-is-pressed-the-light-should-stay-v0-ctncxffwa1h81.png?width=571&format=png&auto=webp&s=c863d7241c47d0c65e6df736bb7ac11d241c18e9)
Help please: When a button is pressed, the light should stay on for 10 clock cycles and then turn off however the light stays on indefinitely... : r/VHDL
![Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count](https://preview.redd.it/does-anyone-know-why-this-vhdl-code-is-not-counting-on-my-v0-3uju1j6xm64a1.png?auto=webp&s=9095f5907457c3b788d495474164595aab1403e7)
Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on "0". So I am assuming it is not making it to the second count
![code design - Difference between If-else and Case statement in VHDL - Electrical Engineering Stack Exchange code design - Difference between If-else and Case statement in VHDL - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/60mk4.png)
code design - Difference between If-else and Case statement in VHDL - Electrical Engineering Stack Exchange
![VHDL elegant way of implementing a select with don't care condition in the input - Electrical Engineering Stack Exchange VHDL elegant way of implementing a select with don't care condition in the input - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/gXoRn.png)